The ADC block converts input voltage within the range of 30 mV to 1030 mV into an 8-bit digital code (min value is 0 for 30 mV and max value is 255 for 1030 mV). The CNT3/DLY3/FSM1 block is configured as a delay that takes counter data from the ADC. This ensures voltage to time delay conversion.

The second part was implemented using 2-bit LUT0 and CNT0/DLY0 blocks. LUT0 was configured as an inverter. The CNT0/DLY0 block is configured as a delay for 19.98 ms (~50 Hz). The combination of these blocks implements a signal generator where its period equals the delay time. 

The third part was implemented with CNT1/DLY1, OSC, CNT2/DLY2/FSM0, and CNT3/DLY3/FSM1 blocks. The CNT1/DLY1 block generates a constant pulse having a width of 0.5 ms which is equal to one of the extreme positions of the servo motor. The OSC and CNT2/DLY2/FSM0 blocks form the clock pulses for CNT3/DLY3/FSM1 block. With these blocks, we can control the pulse width that provides the other extreme position of the servo motor. The CNT3/DLY3/FSM1 block with the maximum counter data of 255 and the frequency (clock) formed by the combination of OSC and CNT2/DLY2/FSM0 blocks provides a pulse width of 2 ms. The functionality waveforms of the design operation are shown in Figure 6 and Figure 7 (Channel 1 is PIN6 (A_IN); Channel 2 is PIN14 (OUT)).

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