IBM’s latest announcement making waves is the introduction of 2 nanometer (nm) nanosheets

IBM didn’t mince words in its release, highlighting four high-visibility, popular applications these devices will impact:

  • Longer cell phone battery life (4x current lifespans!)
  • Faster laptops
  • Lower carbon emissions from datacenters
  • Faster object detection (useful for applications such as autonomous vehicles)

 

IBM’s brand new 2 nm wafer, Image from IBM

 

So we’re all on the same page, 2 nm comparable in length to four silicon atoms. 

 

From 7 nm to 2 nm in 5 Years

In 2015, IBM announced the first working 7 nm chip. IBM credited the achievement to nontraditional semiconductor manufacturing techniques, including the use of silicon germanium (SiGe) channel transistors and extreme ultraviolet (EUV) lithography. 

Even as recently as mid-2020, EUV was considered a stretch for anything below 3nm due to its expense, despite being earmarked as a promising technology for many years. In November of 2020, however, IBM claimed a EUV breakthrough which they claimed firmly extends the capability of single-expose EUV patterning to the 5nm node and below,” and may have played a part in this 2 nm milestone.

2017 brought immediate improvements when IBM revealed that they had innovated a new process for developing 5 nm chips (more on that below).

With this new advancement announced today, IBM asserts that their 2 nm chips use 75% less energy than their current-gen 7 nm counterparts. They also claim 45% “higher performance” as a general term, again compared to current-gen 7 nm chips.

An important note here is that this is not an “and” statement. These chips are being claimed to be able to provide much higher calculation speed OR use much less energy, depending on which spec is prioritized for a given application.

 

A closeup of the new 2 nm wafer. Image from IBM

 

According to IBM, “it shouldn’t be too long” until 2 nm chips become standard after this point. They’ve also predicted that we’ll see the first batch of 2 nm chips rolling off the production line in 2024.

But IBM has made it clear that they intend to continue claiming industry-firsts in the semiconductor industry. Perhaps a word that may need to enter the semiconductor industry’s lexicon more prominently in the next decade is the angstrom, defined as 0.1 nanometers. The hurdles are many and high between this current moment and angstrom-level chips. But it’s also hard to ignore the fact that “Moore’s law is dead” has been a common refrain for many, many years. And yet, here we sit at 50 billion transistors on a chip the size of a fingernail.

 

The Successor to the FinFET: Gate-All-Around

In an accompanying IBM Research blog post, engineers Julien Frougier and Dechao Guo break down some of the nitty gritty involved in the 2 nm milestone. According to them, there were a few of what they term “‘Aha!’ moments” to boost them along their way. 

As we already mentioned, IBM first publicized the Gate-All-Around (GAA) nanosheet architecture in 2017.

 

2 nm nanosheet devices. Image from IBM.

 

IBM characterizes GAA as the successor to the FinFET nanowire technology often credited with getting the industry to the 7 nm level in the first place. As explained in a research paper released for the 2017 Symposium on VLSI Technology Digest of Technical Papers, the key is the large Weff, or effective transistor width, which allows “superior electrostatics and dynamic performance” as compared to scaled FinFETs, even as it benefits from “multiple threshold and isolation solutions inherited from FinFET technologies.”

This shift from nanowires to nanosheets was one of these “‘Aha!’ moments.” Another was the realization that introducing inner spacer modules (structural elements which “define the effective gate length of GAA devices”) into the architecture was key to reducing gate-to-source/drain capacitance.

The authors also highlight the development of a Multi-Vt (multi-threshold-voltage) device that allows developers to select their needed performance by customizing their leakage levels.

 

“High-tech Cookie Sheet” and Other Laymen-friendly Terms

Something which may stand out to engineers as this news sweeps the world is the accessibility of IBM’s announcement. Most of the gory details of the technical side of the breakthrough came in the form of the IBM Research blog post by Frougier and Guo.

Both the context and language of IBM’s public-facing news release and video this morning are much more layman-friendly than those associated with previous breakthroughs. From the beginning, IBM’s newsroom article takes a step back to assert that semiconductors “play a critical role” in familiar—but broad—technologies. In the accompanying video, the narrator explains that semiconductor wafers are akin to a “high-tech cookie sheet.”

Even the applications cited by IBM seem built towards making this news accessible to the general public. Teasing the abilities to enable significantly longer cell phone battery life and faster laptops are clearly meant to make this breakthrough more relatable for non-engineers.

 

IBM Q System One, IBM’s “commercial-use” quantum computer, used as the totem of an example application. Screenshot from IBM

 

This could be an intentional attempt by IBM to court more public buy-in for their efforts. By reaching out to and ultimately educating the average technology user, IBM is effectively changing the way we talk about the deeply complex world of semiconductor research. 

If you had told Gordon Moore in 1965 that transistor technology would be gracing the front page of a mainstream hobbyist magazine like PC Gamer, he probably would have been baffled (and not just because gaming PCs would only become mainstream themselves in the 1980s). We may very well be witnessing a cultural shift that brings the world of EEs closer to the forefront of the public consciousness as never before.


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